A SiC semiconductor device having a JFET with a trench structure has been disclosed, for example, in JP 2003-69041 A or US 2005/0233539 corresponding to JP 2005-328014 A. FIGS. 7A-7C illustrates such a conventional SiC semiconductor device. FIG. 7A is a plan view of the conventional SiC semiconductor device, FIG. 7B is a cross-sectional view taken along the line VIIB-VIIB in FIG. 7A, and FIG. 7C is a cross-sectional view taken along the line VIIC-VIIC in FIG. 7A.
As shown in FIGS. 7A-7C, after a n−-type drift layer J2, a p+-type first gate region J3, a n+-type source region J4 are formed, in turn, on a n+-type SiC substrate J1, a trench J5 penetrating these is formed. Then, an n−-type channel layer J6 and a p+-type second gate region J7 are formed in the trench J5. Although not shown in the drawings, a gate voltage applied to a gate electrode electrically connected to the second gate region J7 is controlled so that a drain current can flow between a source electrode electrically connected to the n+-type source region J4 and a drain electrode electrically connected to the n+-type SIC substrate J1.
In the above-described conventional SiC semiconductor device, as shown in FIG. 7A, each trench J5 has a strip shape, and the trenches J5 are laid out in a stripe pattern. However, it has been confirmed that when the trenches J5 has a strip shape, an excessive drain current flows. FIG. 8 is a characteristic diagram obtained when a drain current characteristic with respect to a gate voltage of the SiC semiconductor device is measured. As can be understood from FIG. 8, when the gate voltage approaches a threshold for driving the JFET, the drain current starts to flow before the gate voltage exceeds the threshold. Due to the drain current occurring near the threshold, an ideal JFET characteristic, in which the drain current does not start to flow until the gate voltage reaches the threshold, cannot be obtained.
It has been confirmed that such a problem can occur not only in a JFET, but also in an accumulation mode MOSFET.